In a conventional level conversion circuit, a positive feedback operation is used. The level conversion circuit includes first and second P channel MOS transistors in which drains and gates of the first and second P channel MOS transistors are cross-coupled each other. Further the first and second P channel MOS transistors are connected to respective drains of first and second N channel MOS transistors as loads. According to the conventional level conversion circuit, when a difference between voltages before and after a level shift becomes large, even if an input signal is inverted, an output signal is not completely inverted. Therefore, the conventional level shift circuit has a problem that the operation becomes unstable.
In order to solve this problem, it is necessary to make a drain current that flows in either one of the first and second N channel MOS transistors, which is rendered conductive by an inverse operation, sufficiently larger than that flowing in either one of the first and second P channel MOS transistors, which is rendered non-conductive, in an early stage of the inverse operation.
Then, although a gate width of the respective first and second N channel MOS transistors is made larger in order to improve a driving capability, a high speed operation is not achieved because a parasitic capacitance increases. Moreover, the above circuit results in increases in a current consumption and a circuit area.
On the other hand, for example, Japanese patent application Laid Open No. 2002-76882 describes a semiconductor integrated circuit device in which a level shift operation is fully conducted even if a ratio of the voltages before and after the level shifts is set large.
The semiconductor integrated circuit device shown in the Japanese patent application includes a level shift circuit having an input node into which an input signal with a first amplitude is inputted, and an output node from which a signal with a second different amplitude is outputted. The level shift circuit carries out a level shift operation of the input signal with the first amplitude to the output signal with the second amplitude. The level shift circuit further includes a current mirror circuit which charges the output node, and a switch circuit which operates the current mirror circuit after the input signal is inverted until the inverse of the output signal is completed.
However, when a frequency of the input signal becomes high, the level conversion circuit shown in the above patent application requires time for stopping the operation of the current mirror circuit, therefore which results in an insufficient inverse of the output signal and a problem of an insufficient operation of the level conversion circuit.